Dual work function devices are becoming increasingly common in CMOS devices to provide enhanced PMOS performance. A transistor consists of a gate, a source, and a drain. In dual work function devices commonly practiced in the art, if the source and drain are doped N+, the polysilicon gate must also be doped n-type. Conversely, if the source and drain are doped P+, the polysilicon gate is doped p-type.
There are several problems which arise when forming a dual work function device. When the polysilicon gate is doped n-type or p-type, the dopant tends to penetrate the gate dielectric and enter the substrate. This limits the processing conditions used to form the device, the choice of a DRAM transfer device, as well as the materials that may be used as the gate dielectric. There are also numerous alignment problems which occur due to the additional implantation of dopants and a corresponding increase in throughput time. Several methods have been proposed for forming dual work function logic devices. However, with the ever increasing circuit densities in ULSI, it is becoming necessary to integrate high performance logic with high density DRAM. Unfortunately, the present technology for forming the gate conductors for high performance logic and high density DRAM is quite different.
FIG. 1 shows a prior art method which separately forms the PFET and the NFET in a dual work function logic device. The source/drain regions 2,3 and gates 4,5 are all doped at the same time. The gates are formed on the wells. As shown in FIG. 1, a photoresist 6 is formed over the p-well 7 and the NFET. A P+ dopant is then implanted in the n-well 8 to form the source/drain regions 2 as well to dope the polysilicon gate 4 P+. The NFET is formed in a similar manner implanting an n-type dopant with photo resist over the PFET.
U.S. Pat. No. 5,770,490 to Frenette et al. describes another method of forming a dual work function logic device. In this method, a first layer of doped material is formed over the entire substrate. The first layer is then removed in selected areas where doping opposite of the first layer is desired and a second layer of an oppositely doped material is formed over the entire surface. Drive in anneal is then performed to diffuse the dopants into the adjacent areas.
U.S. Pat. No. 5,605,861 to Appel proposes a similar solution for forming a dual work function logic device. Here, a layer of glass having a P+ dopant therein is formed over the substrate. This layer is then removed above the p-well and the polysilicon gate layer in this region is then doped n-type. The structure is heated to cause the P+dopant to diffuse from the glass into the polysilicon gate layer over the n-type region.
The known methods for forming high performance logic devices cannot be used to form high density DRAM where the transfer device is a surface channel PFET. It may be advantageous in a logic process to have a surface channel PFET transfer device as the MOSFET for a trench cell. This integrates well with the already existing P+ substrate normally used in high performance bulk silicon logic.
High density DRAM requires an insulating cap which is self-aligned to the gate conductor. This structure is necessary for forming bit line contacts which are borderless to adjacent word lines. A typical high density DRAM is shown in FIG. 2. As can be seen from FIGS. 1 and 2, the present state of the art gate stack for high performance logic device consists of a single polysilicon gate conductor 4,5, whereas the high density DRAM has a multi-layer gate stack 10. The gate stack 10 of the DRAM typically comprises a polysilicon gate conductor 11 with a metal layer 12 formed thereon for lowering the resistance of the polysilicon gate. This gate structure is then entirely enclosed on all sides by a capping layer 13. The capping layer 13 is provided so that the borderless contact stud 14 can be formed on the gate stack 10, without shorting to it. This structure with the borderless contact stud is necessary to achieve the required high densities in DRAM cell arrays.
Current processes for forming logic devices do not provide for a self-aligned insulating cap and DRAM processes are not easily amenable to dual work function gate doping. Therefore, there is a need to provide dual work function gate conductors with a self-aligned insulating cap which can be readily made for merged high performance logic/high density DRAM applications. Additionally, the borderless contact can be applied to logic to increase their standard cell density (e.g. SRAM, adder, etc.)